Electronic design automation (EDA) software systems commonly perform routing of networks of circuit designs, such as clock networks (hereafter, clock nets). Such net routing may be performed using all possible layers (e.g., metal layers) of the circuit design (e.g., full three-dimensional (3D) global routing), but this can result in a slow routing process and no control of quality (e.g., of a clock signal provided by a clock net). Alternatively, net routing may be performed using a predefined range of layers (e.g., between metal layer eight (M8) and metal layer nine (M9)), but strict routing between a predefined range of layers can result in congestion, long wirelength, increased power usage, or lower Quality of Result (QOR).